2013-03-31 21:13:51 -06:00
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#include <stdint.h>
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#include <stdbool.h>
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#include <avr/io.h>
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#include <avr/interrupt.h>
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#include "avr.h"
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2014-01-11 21:02:24 -07:00
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#include "config.h"
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2013-03-31 21:13:51 -06:00
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2013-07-02 19:54:39 -06:00
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/* Clock must be a multiple of 2MHz or there will be clock drift */
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2014-01-11 21:54:50 -07:00
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#define TICK_HZ (CLOCK_HZ / 8 / 64)
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#define TICKS_PER_JIFFY (TICK_HZ / 10)
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2013-06-30 14:57:44 -06:00
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2013-03-31 21:13:51 -06:00
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#define cbi(byt, bit) (byt &= ~_BV(bit))
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#define sbi(byt, bit) (byt |= _BV(bit))
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extern volatile bool tick;
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extern volatile uint32_t jiffies;
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2013-06-30 14:57:44 -06:00
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// Interrupt called every jiffy
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ISR(TIM1_COMPA_vect)
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2013-03-31 21:13:51 -06:00
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{
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2013-06-30 14:57:44 -06:00
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jiffies += 1;
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tick = true;
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2013-03-31 21:13:51 -06:00
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}
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void
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init(void)
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{
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2013-06-30 14:57:44 -06:00
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int i;
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2013-03-31 21:13:51 -06:00
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2013-05-04 19:46:18 -06:00
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DDRA = ~(_BV(NESOUT));
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2013-03-31 21:13:51 -06:00
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DDRB = 0xff;
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2013-06-30 14:57:44 -06:00
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TCCR1A = 0;
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TCCR1B = 0;
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2014-01-11 21:54:50 -07:00
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TCNT1 = 0; // reset counter
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2013-06-30 14:57:44 -06:00
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OCR1A = TICKS_PER_JIFFY - 1;
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2013-07-02 19:54:39 -06:00
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TCCR1B |= _BV(WGM12);
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2014-01-11 21:54:50 -07:00
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TCCR1B |= _BV(CS11) | _BV(CS10); // prescale: clk_io / 64
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2013-07-02 19:54:39 -06:00
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TIMSK1 |= _BV(OCIE1A);
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2013-07-14 07:51:30 -06:00
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bit(PORTA, _BV(7), true);
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2013-06-30 14:57:44 -06:00
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sei();
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2013-03-31 21:13:51 -06:00
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}
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