new design saves 2 pins!
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4d8b3dbafe
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4eea2e956e
27
main.c
27
main.c
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@ -21,17 +21,17 @@ volatile uint16_t jiffies = 0;
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#define SIN BIT1
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#define SCLK BIT2
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#define XLAT BIT3
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#define BLANK BIT4
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#define GSCLK BIT5
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#define bit(pin, bit, on) pin = (on ? (pin | bit) : (pin & ~bit))
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// Connect GSCLK to SCLK
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// Connect BLANK to XLAT
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#define mode(on) bit(P1OUT, MODE, on)
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#define sin(on) bit(P1OUT, SIN, on)
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#define sclk(on) bit(P1OUT, SCLK, on)
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#define xlat(on) bit(P1OUT, XLAT, on)
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#define blank(on) bit(P1OUT, BLANK, on)
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#define gsclk(on) bit(P1OUT, GSCLK, on)
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void
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latch()
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@ -118,10 +118,8 @@ setup_dc()
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int
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main(void)
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{
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int gscount = 0;
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WDTCTL = WDTPW + WDTHOLD; // Disable Watchdog Timer
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P1DIR |= MODE + SIN + SCLK + XLAT + BLANK + GSCLK + BIT6; // P1 output bits
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P1DIR |= MODE + SIN + SCLK + XLAT + BIT6; // P1 output bits
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P1OUT = 0;
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@ -140,22 +138,9 @@ main(void)
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if ((jiffies % 6) == 0) {
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write_num(jiffies / 6, 4);
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gsclk(false);
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latch();
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gscount = 4096;
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pulse();
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}
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if (gscount == 4096) {
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// Pulse BLANK when grayscale clock has cycled 4096 times.
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blank(true);
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blank(false);
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gscount = 0;
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}
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// Pulse the grayscale clock.
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gsclk(true);
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gsclk(false);
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gscount += 1;
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}
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}
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