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hw-rollerderby-scoreboard
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new design saves 2 pins!

This commit is contained in:
Neale Pickett 2013-03-11 20:17:09 -06:00
parent 4d8b3dbafe
commit 4eea2e956e
1 changed files with 6 additions and 21 deletions
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27
main.c
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@ -21,17 +21,17 @@ volatile uint16_t jiffies = 0;
#define SIN BIT1 #define SIN BIT1
#define SCLK BIT2 #define SCLK BIT2
#define XLAT BIT3 #define XLAT BIT3
#define BLANK BIT4
#define GSCLK BIT5
#define bit(pin, bit, on) pin = (on ? (pin | bit) : (pin & ~bit)) #define bit(pin, bit, on) pin = (on ? (pin | bit) : (pin & ~bit))
// Connect GSCLK to SCLK
// Connect BLANK to XLAT
#define mode(on) bit(P1OUT, MODE, on) #define mode(on) bit(P1OUT, MODE, on)
#define sin(on) bit(P1OUT, SIN, on) #define sin(on) bit(P1OUT, SIN, on)
#define sclk(on) bit(P1OUT, SCLK, on) #define sclk(on) bit(P1OUT, SCLK, on)
#define xlat(on) bit(P1OUT, XLAT, on) #define xlat(on) bit(P1OUT, XLAT, on)
#define blank(on) bit(P1OUT, BLANK, on)
#define gsclk(on) bit(P1OUT, GSCLK, on)
void void
latch() latch()
@ -118,10 +118,8 @@ setup_dc()
int int
main(void) main(void)
{ {
int gscount = 0;
WDTCTL = WDTPW + WDTHOLD; // Disable Watchdog Timer WDTCTL = WDTPW + WDTHOLD; // Disable Watchdog Timer
P1DIR |= MODE + SIN + SCLK + XLAT + BLANK + GSCLK + BIT6; // P1 output bits P1DIR |= MODE + SIN + SCLK + XLAT + BIT6; // P1 output bits
P1OUT = 0; P1OUT = 0;
@ -140,22 +138,9 @@ main(void)
if ((jiffies % 6) == 0) { if ((jiffies % 6) == 0) {
write_num(jiffies / 6, 4); write_num(jiffies / 6, 4);
gsclk(false);
latch(); latch();
gscount = 4096; pulse();
} }
if (gscount == 4096) {
// Pulse BLANK when grayscale clock has cycled 4096 times.
blank(true);
blank(false);
gscount = 0;
}
// Pulse the grayscale clock.
gsclk(true);
gsclk(false);
gscount += 1;
} }
} }